Fwd: AMD x2 chips

[Mark Hahn]

> > no, that's obviously not the case - you can see it from the die
> > photos. the cores are clearly laid out as separate blocks - that
> > doesn't mean they're separate ICs, by any normal definition.  for
> > instance, the cores certainly don't have a pad ring and IO drivers,
> > just to connect to the SRQ (another on-die block within the same
> > IC.)
> 
> So in other words, you're talking only _packaging_ differences.
> I'm talking about _functional_ units here.

I'm talking about the physical die: the cores (and memory controller,
and HT controller, and SRT and xbar) are all functional units.
that doesn't make them "separate ICs".

> is timed _differently_ than the core, then yes, I consider it a
> _separate_ IC.  It's just on the same die, moving whatever bus or

OK then, you should know that the rest of the world does not use 
IC that way.

> other arbitration logic inside of the die.

then by your definition of IC, any block or functional unit is 
a separate IC.  so the core has a "FPU" IC, for instance.
or a register-file IC.  you're welcome to use words this way,
but don't expect people to conform.

> If the peripherals are integrated as part of the core, timing and
> lack of other drivers (such as segmentation by a general bus), then
> it's the same IC AFAICT.

this is a bizarre distinction.  timing has nothing at all to do with 
whether something is a separate IC (for instance, double-clocked ALUs
on a P4 would be separate ICs).  what "general bus" means, I can only
guess, but they they don't usually make any sense on-die.

the original DC P4's did actually have a "general bus" on-die,
which is precisely why they present two FSB loads, and received 
a lot of sneering.

> > but you don't seem to be getting the fact that the current HT 
> > has an 8-node limit.  since you can already buy an 8-socket,
> > 16-core machine (without any sort of HT switching or bridging),
> > it's clear that each DC socket acts as a single HT node.  it simply
> > can't somehow have additional HT address range on-chip.
> 
> Then how do you explain more than 16 sockets using the 4 CPU boards
> with HyperTransport connectors between?

I'd appreciate a reference to this 16-socket system; is it somehow 
using the new M2 opterons?  the Horus people clearly think they 
have something unique in their system, which exists precisely to 
do the extra bookkeeping to make HT think there are only 8 nodes,
but still "proxy" them into a single memory address space.

> node from the standpoint of the socket.  I'm merely saying that AMD
> uses HyperTransport inside of the processor, or at least some sort of

there's absolutely no reason to think AMD uses HT "inside" the chip
(presumably between the HT units, core(s) and memory controller.)
it would be pointless to add that generality, complex, and more expensive.

> > that's the topic: AMD's diagrams and Bill's message point out that 
> > within a single AMD DC chip, the memory, HT ports and core(s) are 
> > connected by a non-HT xbar.  the cores are not separately
> > HT-addressable and neither is the dram interface.
> 
> Then what is the xbar?
> Is it EV6?

an xbar is a device which can switch between any of its ports.
there's really no need to refer to Alpha architecture here.
(I have a whole room full of EV6's, and xbar is really a logical
construct, since not every possible connection can be made.)

> I've always wondered if that's what used to connect a single core to
> its memory controller and HyperTransport anyway.

you still didn't look at AMD's diagram?  the connection is 
core->SRQ->xbar->memctrl.

> In any case, the changes have been _minimal_ for AMD AFAICT.  The

correct: another port on the srq.  they even brag about this, how they
had the foresight to design for DC in the original k8.