Fwd: AMD x2 chips

[Bryan J. Smith]

Mark Hahn <hahn at physics.mcmaster.ca> wrote:
> then by your definition of IC, any block or functional unit is 
> a separate IC.  so the core has a "FPU" IC, for instance.
> or a register-file IC.

Huh?  Now I have to _strongly_disagree_.

MEAGs (one-hots) and other control logic do _not_ select registers,
ALU pipes, FPU pipes, etc... across different cores, _only_ in the
same core.  The control logic is not fetching and decoding
instructions for blocks from one core for the _other_ core.

Or are you now just trying to "meet [my] level of knowlege"?
(more like you ass-u-me'd what my "level of knowledge" was ;-)

> you're welcome to use words this way, but don't expect people
> to conform.

And you're over-simplifying.  The crossbar between the cores is
_radically_different_ than between the "blocks."  The control unit of
the cores do _not_ interface.  You're crossing the concepts of
building peripherals around a core with having two _separate_ cores.

I don't know why you're doing that.  I have _no_ position.  I'm just
trying to say that the cores are virtually _separate_ ICs.  At least
from the standpoint of _whatever_ the crossbar is -- which seems to
be _no_different_ whether it is single _or_ dual-core (or multi-core
for that matter).

Which is why no special support is required, sans maybe APIC register
setup and other details -- which is what a BIOS update provides.

> this is a bizarre distinction.  timing has nothing at all to do
> with whether something is a separate IC (for instance,
> double-clocked ALUs on a P4 would be separate ICs).

I meant from the standpoint of _scheduling_ instructions for a
pipelines.  And as I stepped back a bit in this e-mail, I really
meant anything driven by and integrated around the control logic.

> what "general bus" means, I can only guess, but they they don't
> usually make any sense on-die.

I only said it because you tell me what "busses" and "arbitration
logic" fits your definition.

> the original DC P4's did actually have a "general bus" on-die,
> which is precisely why they present two FSB loads, and received 
> a lot of sneering.

Okay, I didn't know that.  My ignorance there.

> I'd appreciate a reference to this 16-socket system; is it somehow 
> using the new M2 opterons?  the Horus people clearly think they 
> have something unique in their system, which exists precisely to 
> do the extra bookkeeping to make HT think there are only 8 nodes,
> but still "proxy" them into a single memory address space.

I'm talking about the modular 4-socket mainboards that can be
combined into 16 (or greater) sockets.  The 4-socket uses 2
HyperTransports between each CPU, and then 2-sockets have 1
HyperTransport to the next board (ignoring the HyperTransport links
used for I/O).  The common configuration I've seen is 4 x 4-socket
mainboards.

  O---O+++O---O
  |   |   |   |
  O---O   O---O
  +           +
  +           +
  O---O   O---O
  |   |   |   |
  O---O+++O---O 

> there's absolutely no reason to think AMD uses HT "inside" the chip
> (presumably between the HT units, core(s) and memory controller.)
> it would be pointless to add that generality, complex, and more
> expensive.

Okay, then what is it?
How does it appear?  Inside?  Outside?

Furthermore, how does even the _single_ core+L1+L2 talk to the
on-board memory and HyperTransport?  Is that a Xbar too?  Possible an
internal implementation of EV6?

Everything I've read suggests that there are _no_changes_ in the
dual-core from the single-core.  Which suggests there is the same
switch used inside.

> an xbar is a device which can switch between any of its ports.
> there's really no need to refer to Alpha architecture here.
> (I have a whole room full of EV6's, and xbar is really a logical
> construct, since not every possible connection can be made.)

Okay then, virtually up to a 16-node Xbar (even if not physical).

The 40-bit address and other bus limitations of EV6 are readily
apparent in A64/Opteron, which suggests that other than the 64-bit
ALU, PAE 52-bit "Long Mode" and 8 new XMM registers, A64/Opteron is
little changed at the core from Athlon and its EV6.

Which suggests they moved the Xbar inside.
Which is why going dual and even multicore is easy.

And I've been searching for a _long_time_ to find out what is
actually at work.

> you still didn't look at AMD's diagram?  the connection is 
> core->SRQ->xbar->memctrl.

And what is the SRQ/Xbar?

> correct: another port on the srq.  they even brag about this, how
> they had the foresight to design for DC in the original k8.

Which is what?  Is it just a new implementation of EV6 on-die?
Everything I've read suggests so.

My apologies for calling it "HyperTransport."
I have to speculate because this info has been hard to come by.


-- 
Bryan J. Smith     Professional, Technical Annoyance
b.j.smith at ieee.org      http://thebs413.blogspot.com
----------------------------------------------------
*** Speed doesn't kill, difference in speed does ***