Fwd: AMD x2 chips (Clarification)

[Bryan J. Smith]

"Bryan J. Smith" <b.j.smith at ieee.org> wrote:
> The 40-bit address and other bus limitations of EV6 are readily
> apparent in A64/Opteron, which suggests that other than the 64-bit
> ALU, PAE 52-bit "Long Mode" and 8 new XMM registers, A64/Opteron is
> little changed at the core from Athlon and its EV6.

Let me rephrase/clarify that ...

"little changed at the core from Athlon MP and its EV6 -- and
especially the local AGPgarts, which are now full I/O MMUs"

There is so much EV6 footprint around A64/Opteron that drawing the
conclusions are unavoidable.  I've been searching but I'm sure AMD
isn't about to admit they reused a lot of ideas.

Especially when they can market the partial-mesh interconnect of
HyperTransport.  I sure wish they'd just come out and say whether the
Xbar and the A64/Opteron core has lineage to EV6's Xbar.  That would
finally explain a LOT (or at least CONFIRM it).


-- 
Bryan J. Smith     Professional, Technical Annoyance
b.j.smith at ieee.org      http://thebs413.blogspot.com
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*** Speed doesn't kill, difference in speed does ***